Slides from webinar: ARM AAME Essentials

'ARM AAME Essentials' was ended!
For those who missed something, we are going to publish a round up of slides and questions asked at the end of today's webinar section (sorry if we missed something).

We hope in your interest. See you to the next ARM webinar!

Audience questions:

D: can you explain tail chaining in detail?
R: Sure, the idea of tail chaining is to reduce the time it takes to go from the end onf an executing interrupt sub routing to the begining of a starting sub routine. WIth a cortex-M the time is arround 6 cycles because cortex-M do not pop and push context register for no reasons. Other ARM core do not have this nice feature hence it takes >20 cycles to achieve the same thing.

D: a non technical queston over here... is the webinar recording available for our reference later as well?
R: Yes we will send you a link to the recording early next week.

D: in our simulation,  a hardfault handler will be triggered and entered when a single Bus error occurs. my understanding it is not correct,  the bus fault handler should be triggered, intead of hard fault handler.   May I ask your suggestion for debugging ? Thanks ! 
R: Sure HardFault handler is triggered through fault escalation. By defauld memory fault/bus fault are disabled hence the core escalades the fault to a hardfault. Check if you manually enabled the bus faults/memory faults in your reset handler.

D: Can you explain a bit more about dynamic clock management with SysTick?
R: The systick timer can use  the core's clock (default) but it can also be programmed to use an external clock source this is something that needs to be enabled at the SoC level. the limitation is that the external clock must be at least 2.5 times slower than the core clock since the external clock signal works like a clock enable. If you wanted to have a dynamical clock you would have to use the external clock source (an a clock factory with PLLs and the likes).

D: What are the advantages of Bit Banding?
R: Bid banding allows to do a single bit read modify write atomic operation which cannot normaly be achieve with a RISC core.

D: may I know which M4 register should be check, System Handler Priority Registers?
R: I am not sure what you mean my system Handler priority register?


D: It was mentioned that ARM architecture is of load/store type, thus having separate instructions for reading and writing data. How does it handle atomic operations like a semaphore for multi-processor accesses?
R: Very good question! Cortex-M use dedicated instruction + hardware to implement LDREX/STREX load and store exclusive. In addition bit banding also enable this. with bit banding when you write to a dedicated memory region this operaton is translated into a locked read/write transaction on the bus that in turns achieve the required atomicity.

C/D: I have a complex question. Are there instructions to enable the multicore processing? or parallel core processing? For example with RTOS?
R: In Cortex-M you do not have multicore processing. Other ARM cores such as Cotex-A9 Cortex-A15 have a desicated bit (SMP) part of cp15 that you would have to set to enable coherency management in an MPCore implementation.

D: What limitations does the ARM core have when they are used as on-chip procesors on FPGAs?
R: Not limitations as such. Obviously the max frequency is generally fixed and you hve to use the AHB lite protocol to comminicate with the rest of the system but noting that could be seen as a real limitation.

D: how to enable/active bus fault handler in the reset handler?  if SHCSR should be set ?
R: I can't remember from the top of my head I would have to look up the TRM to give you a precise answer.

D: It is used on Altera FPGAs more than Xilinx. Why is that?
R: Numerous FPGA vendors offer hard core solutions each targetting different industrial segments.

D: Which external bus types are supported by Cortex family?
R: That's a long story but for the cortex-M we use AMBA AHB Lite for ICODE/DCODE/SYSTEM as well as the APB bus for coresight debug component External private peripherals.